The present invention is generally related to phase lock loop (PLL) demodulators and more particularly to systems and methods for utilizing feed-forward tracking error compensation to address tracking error in a PLL demodulator.
Phase locked loops (PLLs) are devices that generate a signal and that lock their phase to the phase of an input reference signal. According to the prior art, as shown in FIG. 1, PLL 100 typically has three main components: voltage-controlled oscillator (VCO) 101, phase detector 102, and loop filter 103. VCO 101 generates a signal that has a frequency proportional to the tuning voltage input. This proportionality is typically expressed as a VCO gain parameter (Kv) denoted in units of radians/second per volt. Reference signal 104 may be provided at a reference frequency and phase. Phase detector 102 generates an output voltage proportional to the phase difference between the reference signal and the VCO signal. This proportionality is typically expressed as a phase detection gain parameter (Kd) denoted in units of volts/radian. Thus, phase detector 102 generates a phase error signal (i.e., the phase tracking error). Loop filter 103 amplifies and filters this error signal, which is then fed back to VCO 101. This feedback adjusts the phase of VCO 101 and causes VCO 101 to approximate the phase of the reference signal thereby minimizing the error.
PLL 100 as shown in FIG. 1 is difficult to analyze on a mathematical basis, because the input and output of the loop filter are different types of variables (i.e., voltage proportional to phase and voltage proportional to frequency, respectively). By definition, phase is the time integral of frequency. Therefore, an ideal VCO 200 may be modeled as two mathematical blocks: ideal integrator 201 and ideal voltage to phase transducer 202 as shown in FIG. 2 according to the prior art. Ideal VCO 200 may be incorporated in a PLL system to provide useable PLL model 300 as shown in FIG. 3 according to the prior art. PLL model 300 may then be analyzed according to mathematical model 400 shown in FIG. 4 according to the prior art. In mathematical model 400, Kd represents the phase detection gain parameter of phase detector 102, F(s) represents the transfer function of loop filter 103 (expressed in Laplace transform notation), 1/s represents the transfer function of ideal integrator 201 (also expressed in Laplace transform notation), and Kv represents the VCO gain parameter of VCO 101. The loop gain is represented by the parameter G which equals KdKvF(s)/s. Moreover, xcex8vco represents the phase of the signal produced by VCO 101 and xcex8ref represents the phase of the reference signal. The relationship between xcex8vco and xcex8ref may be represented by the following equation: xcex8vco/xcex8ref=G/(1+G). Thus, when the loop gain is relatively large (G  greater than  greater than 1), xcex8vco approximates xcex8ref with a significant degree of accuracy.
Integrator 201 acts as a low pass filter and causes the loop gain to decrease with increasing frequency. Thus, tracking error increases with increasing frequency. At some frequency, the loop gain falls below unity. Above this frequency (which defines the loop bandwidth), the loop has relatively little response to the reference stimulus and, hence, limits the capacity of PLL 100 to continue accurately tracking the reference signal. Accordingly, this places a constraint upon the bandwidth of modulation that may be applied to the reference signal. Theoretically, the loop bandwidth can be increased by increasing the loop gain. However, in practice, implementations of VCO 101 have finite modulation bandwidth. The limited bandwidth of VCO 101 may be modeled in VCO 500 as a parasitic low pass filter 501 defined by transfer function P(s) as shown in FIG. 5 according to the prior art. This has the effect of modifying the mathematical model by adding another low pass function to loop model 600 as shown in FIG. 6 according to the prior art. As shown in FIG. 6, the loop gain (G) equals KdKvF(s)P(s)/s. This has the practical effect of limiting the loop bandwidth to a relatively small fraction of the VCO bandwidth. Because of numerous design constraints associated with implementations of VCO 101, the VCO bandwidth cannot be made arbitrarily high. Accordingly, the VCO bandwidth often becomes a limiting factor on loop bandwidth. In addition to the VCO bandwidth, the loop filter may have its own bandwidth limitations, especially if it utilizes active circuitry. The effect of finite loop filter bandwidth is the same as VCO bandwidth in terms of limiting loop bandwidth.
PLLs are commonly utilized to build frequency or phase demodulators. A demodulator is a system driven by a modulated signal that produces an output voltage that is proportional to the modulation. FIG. 7 depicts PLL frequency demodulator 700 according to the prior art. VCO 101 tracks the phase of the reference signal. Because of the close mathematical relationship between phase and frequency, VCO 101 also tracks the frequency of the reference. Since the tuning voltage applied to VCO 101 is proportional to the VCO frequency (and, hence, to the reference frequency), the tuning voltage is used directly as demodulated output 701.
FIG. 8 depicts phase demodulator 800 according to the prior art. Phase demodulator 800 is substantially the same as frequency demodulator 700 except that leaky integrator 801 has been added to convert the tuning voltage (proportional to frequency) into a voltage (demodulated output 802) proportional to phase. Since an ideal integrator is not physically realizable, a so-called xe2x80x9cleakyxe2x80x9d integrator 801 is shown, Specifically, leaky integrator 801 approximately acts as an ideal integrator above a specified minimum frequency (xcfx891). Below that frequency, leaky integrator 801 changes to a flat gain versus frequency characteristic. This imparts a low frequency cutoff to the frequency response of the demodulation output port.
In an embodiment, the present invention is directed to a PLL phase demodulator that utilizes feed-forward error correction. The feed-forward error correction may occur by calibrating an equalizer to possess a transfer function that emulates the modulation response curve of the VCO of the PLL phase demodulator. In operation, the equalizer may receive the filtered and integrated version of the error signal produced by the phase detector of the PLL. The equalizer filters the received signal according to the calibrated transfer function. The output of the equalizer is provided to a adder to combine the equalized signal with the error signal produced by the phase detector. The combined signal represents the demodulated output signal. In other embodiments, a similarly calibrated equalizer may be utilized to address tracking error in a frequency demodulator. By utilizing a suitable calibrated equalizer, embodiments in accordance with the invention enable demodulators to operate at arbitrarily high modulation frequencies (for small modulation index) that are not limited by the loop bandwidth or VCO bandwidth.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims. The novel features which are believed to be characteristic of the invention, both as to its organization and method of operation, together with further objects and advantages will be better understood from the following description when considered in connection with the accompanying figures. It is to be expressly understood, however, that each of the figures is provided for the purpose of illustration and description only and is not intended as a definition of the limits of the present invention.